Using ISE's new parser for VHDL on old hardware

So, I'm not for sure why, but no one told me this was possible.

Basically, for the uninitiated, Xilinx's XST synthesizer has 2 parsers in it.

  1. Old -- Runs anytime an older hardware target is selected(such as Spartan 3E). Really slow, useless error messages, doesn't parse seemingly obvious VHDL
  2. New -- Runs anytime a newer hardware target is selected (such as Spartan 6). Really awesome, comparable to ghdl in it's parsing abilities, gives slightly more useful error messages

So, how do you use this shiny new parser on old hardware? There is a hidden "advanced" option.

Right click on the synthesis process. Go to process properties. At the bottom there should be "property display level", make sure to change that to "advanced". Now, scroll all the way down under synthesis options and there should be a box to put in an extra command line argument labeled "Other XST command line options". Now, put in that box this text:

-use_new_parser  yes

Now, magically your obvious VHDL will synthesize to what you intend! For instance, I came across this trick when trying to synthesize the dual port asymmetric block RAM code example straight from the code templates provided with ISE! It would synthesize to distributed RAM instead of block RAM everytime. So, I put in this magical option to use the new parser, and poof. Now it synthesizes to a block RAM without any code changes.

It really makes you wonder why they don't just use the new parser by default for old hardware.

Posted: 9/8/2012 3:26:28 PM

TinyCPU -- My attempt at a processor

Well, one of my life goals (according to my CV) is to create my own processor in an FPGA.

Well, I've finally set out to accomplish this goal. So far, VHDL has been very mind expanding. Things happen sequentially, yet at the same time. Wrapping your head around it can probably be compared to understanding recursion in programming terms.

But anyway, I've finally got to where I can synthesize my CPU design and put it in an FPGA, load it's internal memory from an mbed/arduino/whatever and finally execute a stream of instructions... Of course it's not done, the only instruction supported right now is mov reg, immediate.. but it's a start. There is still a ton of work to be done with it, but hopefully it should be halfway usable as a processor in the next week or two.

If you're curious about the source code of my TinyCPU project, the code is at opencores

For reference, TinyCPU has the following goals:

  1. Mostly single cycle instructions
  2. Von Neumann architecture (code is data and vice-versa)
  3. 8-bit processor (8 bit registers and operations)
  4. 16-bit address bus (capable of accessing it by using segment registers similar to the 8086)
  5. Be simple code and it has to fit within my 250K gate Spartan 3E
Posted: 5/17/2012 12:48:00 AM

VHDL Coding

It's been about 2 weeks since I set out to conquer VHDL and I think I'm finally to the point to where I can say I'm familiar with VHDL. Still learning a lot with each piece of code though.

Basically the learning curve of VHDL is so steep not because of VHDL as a language, but rather because describing hardware is much different from creating software. There is no real easy way to get over the learning curve either without persistence and practice.

So anyway, now as a learning project I'm making a super tiny CPU for my FPGA. I both hate and love VHDL. There is a ton of boiler plate code it seems like, and yet it's so powerful and expressive in describing hardware.

For instance, my simple register file for my CPU totals up to only 30 lines of code... and now imagine describing such a circuit with just logic gates as a circuit drawing:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all; 

entity registerfile is
  port(
    Write:in std_logic_vector(7 downto 0); --what should be put into the write register
    SelRead:in std_logic_vector(2 downto 0); --select which register to read
    SelWrite:in std_logic_vector(2 downto 0); --select which register to write
    UseWrite:in std_logic; --if the register should actually be written to
    Clock:in std_logic;
    Read:out std_logic_vector(7 downto 0) --register to be read output
  );
end registerfile;

architecture Behavioral of registerfile is
  type registerstype is array(0 to 7) of std_logic_vector(7 downto 0);
  signal registers: registerstype;
begin
  writereg: process(Write, SelWrite, UseWrite, Clock)
  begin
    if(UseWrite='1') then
      if(rising_edge(clock)) then
    registers(conv_integer(SelWrite)) <= Write;
      end if;
    end if;
  end process;
  Read <= registers(conv_integer(SelRead));
end Behavioral;

Honestly, it might should be more complicated than I made it, but I can already tell describing hardware in VHDL is going to be much easier than describing it in kcircuit.

Also, I actually have found that following TDD principles makes a lot of sense when describing hardware. Writing tests first shows you quickly how many possible ways your component will be used and allows you to develop and make sure it satisfies all of your needs.

I've never wrote tests first in software, but in hardware it actually seems more intuitive than writing them later.

Posted: 4/29/2012 2:44:22 AM

Recent Projects

Being unemployed really sucks because all of the days kind of just turn into a blur.. but, on the bright side I have a ton of time for side projects. So coming up are a full blog entry(ies) over these two topics:

First, my FM transmitter built from an Arduino, an NS73M, a 4-digit serial 7-segment display, a salvaged car USB charger, 3 push buttons, and a few odd capacitors and resistors. Parts ended up costing me $40, took me about a week to code up my "just-get-this-to-freaking-work-so-I-have-music" code. It's still not done, but it's functional enough for me and I never have a static problem with it like most of the FM transmitters you'll buy at Wal-Mart. The only big thing I need to do now is refactor my code and design a (my first) PCB for it.

Second, hopefully some kind of VHDL project. I finally got done reading Free Range VHDL. Very good book as an introduction to VHDL and I got WebPack installed on my computer again for my FPGA. So hopefully, I'll have a tiny 4-bit processor or something built in a few weeks.

Anyway, I'll get around to actually documenting what I've been doing in a few days hopefully.

Posted: 4/23/2012 8:37:07 PM

My very own CPU

I've decided to finally start doing the proper thing with my VHDL learning and put it in source control.

My current project with it is a very simplistic 4 bit CPU. It is named Earlz' Minimalistic Processor... or EMP for short. It's crap, yes. But it should be simple to implement. You can check out the source code at svn://lastyearswishes.com/emp

Posted: 4/3/2011 6:58:36 PM

VHDL and TDD

So I'm finally actually learning VHDL. It's not so bad as I thought, but I much prefer developing in ghdl rather than the 8 gig bloated barrel of slime named WebPack.

Anyway, one of the things I've noticed is that TDD seems to go very in hand with hardware description languages. I mean, you can toggle switches(practically) or you can create a good, comprehensive test bench. I'm actually going to maybe experiment with making test benches before actual components and see how it goes.

My only complaint is that VHDL isn't all that clean and requires quite a bit of repetition and tedium to write tests in.

Tags: vhdl tdd fpga woot
Posted: 4/2/2011 6:31:22 PM