Using ISE's new parser for VHDL on old hardware

So, I'm not for sure why, but no one told me this was possible.

Basically, for the uninitiated, Xilinx's XST synthesizer has 2 parsers in it.

  1. Old -- Runs anytime an older hardware target is selected(such as Spartan 3E). Really slow, useless error messages, doesn't parse seemingly obvious VHDL
  2. New -- Runs anytime a newer hardware target is selected (such as Spartan 6). Really awesome, comparable to ghdl in it's parsing abilities, gives slightly more useful error messages

So, how do you use this shiny new parser on old hardware? There is a hidden "advanced" option.

Right click on the synthesis process. Go to process properties. At the bottom there should be "property display level", make sure to change that to "advanced". Now, scroll all the way down under synthesis options and there should be a box to put in an extra command line argument labeled "Other XST command line options". Now, put in that box this text:

-use_new_parser  yes

Now, magically your obvious VHDL will synthesize to what you intend! For instance, I came across this trick when trying to synthesize the dual port asymmetric block RAM code example straight from the code templates provided with ISE! It would synthesize to distributed RAM instead of block RAM everytime. So, I put in this magical option to use the new parser, and poof. Now it synthesizes to a block RAM without any code changes.

It really makes you wonder why they don't just use the new parser by default for old hardware.

Posted: 9/8/2012 3:26:28 PM

My very own CPU

I've decided to finally start doing the proper thing with my VHDL learning and put it in source control.

My current project with it is a very simplistic 4 bit CPU. It is named Earlz' Minimalistic Processor... or EMP for short. It's crap, yes. But it should be simple to implement. You can check out the source code at svn://

Posted: 4/3/2011 6:58:36 PM


So I'm finally actually learning VHDL. It's not so bad as I thought, but I much prefer developing in ghdl rather than the 8 gig bloated barrel of slime named WebPack.

Anyway, one of the things I've noticed is that TDD seems to go very in hand with hardware description languages. I mean, you can toggle switches(practically) or you can create a good, comprehensive test bench. I'm actually going to maybe experiment with making test benches before actual components and see how it goes.

My only complaint is that VHDL isn't all that clean and requires quite a bit of repetition and tedium to write tests in.

Tags: vhdl tdd fpga woot
Posted: 4/2/2011 6:31:22 PM